While users can still capitalize on Performance-cores (P-cores) and Efficient-cores (E-cores) to manage their multitasking, new Low-power E-cores have also been added to the team.
With P-cores, E-cores, and new Low-power E-cores, 3D performance hybrid architecture is optimized for performance and efficiency. Let's explore the inner workings of 3D performance hybrid architecture showcased in AI-accelerated Intel® Core™ Ultra processors!
While previous Intel® Core™ processors utilize a single die, all-new Intel® Core™ Ultra processors are built with four tiles. Instead of having the CPU, GPU, and NPU on the same die, these entities have been separated and placed on individual tiles.
Although P-cores and E-cores can still be found on the Compute Tile, the latest Low-power E-cores are built onto the SoC Tile.
On the main Compute Tile of Intel® Core™ Ultra processors, there are still P-cores and E-cores that can be used individually or together in the traditional performance hybrid architecture.
As the business grows it starts to diversify, and you start taking smaller deliveries that barely utilize the van capacity. To help with smaller deliveries, you decide to invest in smaller vehicles to fulfill those smaller orders alongside your large orders. This hybrid approach allows you to adapt to evolving demands efficiently.
In terms of computing, this analogy demonstrates the importance of incorporating different types of cores (P-cores and E-cores) to handle large and small demands.
Located on the SoC Tile, Low-power E-cores are great for offloading background tasks and assisting with multithreaded performance. By having Low-power E-cores, the NPU, memory control, and media on the SoC Tile, these systems can run more efficiently.
In tech terms, this means that the SoC Tile can handle small, background workloads. This frees up the Compute Tile to either handle a different task or go into a lower power mode from not being engaged.
On an Intel® Core™ Ultra processor-based PC, watching a video would only utilize the media section of the SoC Tile. As a user watches their favorite show on Netflix, Low-power E-cores run the streaming. Meanwhile, the Compute Tile holding the P-cores and E-cores is not engaged, helping save power!
Now with cores on the Compute Tile and SoC Tile, the Intel® Thread Director is equipped to communicate between tiles. The Intel® Thread Director allocates the best cores and threads available to work on specific tasks at hand.
Once the user has finished gaming and ends their demanding task, the Intel® Thread Director could move the music workload to the Low-power E-cores. By shifting the task from the Compute Tile to the SoC Tile, the Low-power E-cores are utilized to conserve power . Since it’s not being used, the Compute Tile can then shift into a lower power or no power mode in to further reduce power consumption.
New Low-power E-cores located on the SoC Tile can work on small tasks in the background. By not engaging the powerful Compute Tile, efficiency can be increased.
With an enhanced Intel® Thread Director optimizing performance across cores and tiles, powerful, AI accelerated Intel® Core™ Ultra processors are a great choice for customers!
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